Correctness of the Stability of the 42 Compressor Cell for Partial Product Reduction in Parallel Multiplier Circuits

– Because calculation models of arithmetic logic units based on many-sorted algebras have been proposed, we continue to verify the structure and design of these circuits using the Mizar proof checking system. To evaluate our formal veri cation method on a real production calculation circuit, we describe the formalization of the concept of the 4–2 compressor as a four-inputs–two-outputs binary addition cell (FTAC), to de ne the structures of calculation units for a very fast multiplication algorithm for VLSI implementation. We de ne the circuit structure of four types of FTACs, TYPE-0 to TYPE-3, using the series constructions of the Generalized Full Adder Circuit (GFAC), which generalizes the adder to have positive and negative weights for each input and output. We then successfully prove the circuit stability of the calculation outputs after four steps. The motivation for this research is to establish a technique based on formalized mathematics and its application to calculation circuits with high reliability.